1. Technical Field
The present invention relates to a method and structure for coupling a semiconductor chip to a substrate by use of solder joints, and more particularly to a method and structure for forming an underfill between the semiconductor chip and the substrate, wherein the underfill encapsulates the solder joints.
2. Related Art
A structure of a chip joined to a substrate by solder joints may have underfill material that encapsulates the solder joints and fills a space between the chip and the substrate. With the underfill present, however, the structural integrity of the solder joints are at risk during thermal cycling operations because of tensile stress on the solder joints and shear stress on the solder joints and at the underfill-chip interface.
The tensile stress on the solder joints is due to a difference in coefficient of thermal expansion (CTE) between the chip and the substrate in the vicinity of the solder joints, which causes flexing of the chip and consequent solder joint fatigue leading to loss of contact between chip and the substrate at solder joint locations. The chip CTE is typically about 2 to 5 parts per million (ppm) per xc2x0 C., and the substrate CTE is typically significantly higher (e.g., about 18 to 20 ppm/xc2x0 C.).
The shear stress on the solder joints may be caused by CTE mismatch between the solder joints and the underfill, which may result in solder joint cracking. The CTE of solder joints is typically about 26 to 30 ppm/xc2x0 C., while the CTE of the underfill is typically much higher (e.g., about 70 to 80 ppm/xc2x0 C.).
The shear stress at the underfill-chip interface may be caused by CTE mismatch between the solder joints and the underfill. The shear stress at the underfill-chip interface may result in delamination of the underfill at the underfill-chip interface, causing crack formation at the solder joints.
Thus, there is a need for a method and structure which, during thermal cycling operations, protects the structural integrity of the solder joints that join the chip to a substrate, where an underfill material encapsulates the solder joints and fills the space between the chip and the substrate.
The present invention provides an electronic structure, comprising:
a substrate;
an electronic device coupled to the substrate by an electrically conductive interconnect; and
an underfill disposed in a space between the electronic device and the substrate, wherein an upper portion of the underfill is adjacent to the electronic device, wherein a lower portion of the underfill is adjacent to the substrate, wherein the underfill encapsulates the electrically conductive interconnect, wherein the underfill comprises a resin and a filler, wherein the density of the filler is less than the density of the resin, and wherein the weight percent concentration of the filler in the underfill is higher in the upper portion of the underfill than in the lower portion of the underfill.
The present invention provides a method for forming an electronic structure, comprising:
providing a substrate with a conductive pad coupled to the substrate;
providing an electronic device with a solder member coupled to the electronic device;
soldering the solder member to the conductive pad to form an electrically conductive interconnect that couples the electronic device to the substrate, wherein the solder member is transformed into a solder portion of the electrically conductive interconnect;
dispensing an underfill in a space between the electronic device and the substrate, wherein an upper portion of the underfill is adjacent to the electronic device, wherein a lower portion of the underfill is adjacent to the substrate, wherein the underfill encapsulates the electrically conductive interconnect, wherein the underfill comprises a resin and a filler, and wherein the density of the filler is less than the density of the resin; and
heating the underfill after which a weight percent concentration of the filler in the underfill is higher in the upper portion of the underfill than in the lower portion of the underfill.
The present invention provides a method for forming an electronic structure, comprising:
providing a substrate with conductive pads coupled to the substrate;
providing an electronic device with a solder members coupled to the electronic device;
dispensing an underfill on the substrate and over the conductive pads, wherein the underfill comprises a resin and a filler, and wherein the density of the filler is less than the density of the resin;
moving the electronic device toward the substrate and into the underfill such that the solder members of the electronic device are aligned over corresponding conductive pads of the substrate, said moving occurring until the solder members are proximate the corresponding conductive pads; and
heating the electronic device resulting in soldering the solder members to the corresponding conductive pads to form electrically conductive interconnects that couple the electronic device to the substrate, wherein the solder members are each transformed into a solder portion of the electrically conductive interconnect, wherein after the heating a weight percent concentration of the filler in the underfill is higher in an upper portion of the underfill that is adjacent to the electronic device than in a lower portion of the underfill that is adjacent to the substrate.
The present invention provides a method and structure which, during thermal cycling operations, protects the structural integrity of the solder joints that join the chip to a substrate, where an underfill material encapsulates the solder joints and fills the space between the chip and the substrate.